Description ■UJTAG: The timing model of most output signals from the UJTAG to the fabric were updated to be triggered on the falling edge of the clock rather than the rising edge. The reset signal fab_uj_trstb
Read moreDescription ■This is a Customer Advisory Notification. DDR3 and DDR4 pin assignments of the RTPF500T-CG1509 package have been altered in Libero SoC v12.5. Place and route performed with Libero SoC v12.4
Read moreDescription ■A change has been implemented to the PolarFire two-port large SRAM configurator and dual-port large SRAM configurator. The LSRAM configurator engine for the Write Byte Enable selection divides
Read moreDescription ■A change has been implemented to the PolarFire two-port large SRAM configurator dual-port large SRAM configurator and CoreFIFO. The LSRAM configurator engine correctly generates asymmetric
Read moreDescription ■With Libero SoC v12.5 Libero SoC v12.5 SP1 and Libero SoC v11.9 SP6 netlist tie-off information is now correctly being passed to SmartTime for a complete static timing analysis. Reason for
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